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09/18/2023
From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches
Formal property verification (FPV) has existed for decades and has been ...
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04/19/2023
Massive Data-Centric Parallelism in the Chiplet Era
Recent works have introduced task-based parallelization schemes to accel...
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01/07/2023
Duet: Creating Harmony between Processors and Embedded FPGAs
The demise of Moore's Law has led to the rise of hardware acceleration. ...
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07/26/2022
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications
Applications with low data reuse and frequent irregular memory accesses,...
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10/21/2021
Evolving Transferable Pruning Functions
Channel pruning has made major headway in the design of efficient deep l...
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10/21/2021
Class-Discriminative CNN Compression
Compressing convolutional neural networks (CNNs) by pruning and distilla...
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04/08/2021
AutoSVA: Democratizing Formal Verification of RTL Module Interactions
Modern SoC design relies on the ability to separately verify IP blocks r...
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04/29/2020
Rethinking Class-Discrimination Based CNN Channel Pruning
Channel pruning has received ever-increasing focus on network compressio...
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11/20/2018
JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
Energy efficiency has become an increasingly important concern in comput...
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12/21/2017
