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09/07/2023
Mapping of CNNs on multi-core RRAM-based CIM architectures
RRAM-based multi-core systems improve the energy efficiency and performa...
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08/18/2023
parti-gem5: gem5's Timing Mode Parallelised
Detailed timing models are indispensable tools for the design space expl...
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08/04/2023
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Despite its ever-increasing impact, security is not considered as a desi...
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08/03/2023
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories
Emerging non-volatile memories (NVMs) represent a disruptive technology ...
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04/12/2023
Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic
Most chip designers outsource the manufacturing of their integrated circ...
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04/12/2023
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules
Novel non-volatile memory (NVM) technologies offer high-speed and high-d...
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11/30/2022
Quantitative Information Flow for Hardware: Advancing the Attack Landscape
Security still remains an afterthought in modern Electronic Design Autom...
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07/22/2022
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
The increasing complexity of systems-on-a-chip requires the continuous d...
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07/21/2022
PA-PUF: A Novel Priority Arbiter PUF
This paper proposes a 3-input arbiter-based novel physically unclonable ...
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06/23/2022
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs
Networks-on-Chips (NoCs) recently became widely used, from multi-core CP...
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03/10/2022
Designing ML-Resilient Locking at Register-Transfer Level
Various logic-locking schemes have been proposed to protect hardware fro...
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12/24/2021
A Parallel SystemC Virtual Platform for Neuromorphic Architectures
With the increasing interest in neuromorphic computing, designers of emb...
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09/06/2021
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog
The enormous amount of code required to design modern hardware implement...
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07/19/2021
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks
Logic locking has emerged as a prominent key-driven technique to protect...
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07/05/2021
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
In the past decade, a lot of progress has been made in the design and ev...
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01/17/2021
Brightening the Optical Flow through Posit Arithmetic
As new technologies are invented, their commercial viability needs to be...
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01/14/2021
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
With the growing demands of consumer electronic products, the computatio...
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01/05/2021
An Investigation on Inherent Robustness of Posit Data Representation
As the dimensions and operating voltages of computer electronics shrink ...
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12/23/2020
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
The everlasting demand for higher computing power for deep neural networ...
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11/20/2020
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
Logic locking is a prominent technique to protect the integrity of hardw...
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06/18/2020
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect
Machine intelligence, especially using convolutional neural networks (CN...
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05/30/2020
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
Many engineering and scientific applications require high precision arit...
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04/10/2019
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration
In recent years, neural networks have surpassed classical algorithms in ...
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03/14/2018
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization
We present efficient realization of Generalized Givens Rotation (GGR) ba...
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05/07/2013
