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02/02/2021
MANA: Microarchitecting an Instruction Prefetcher
L1 instruction (L1-I) cache misses are a source of performance bottlenec...
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12/30/2018
ORIGAMI: A Heterogeneous Split Architecture for In-Memory Acceleration of Learning
Memory bandwidth bottleneck is a major challenges in processing machine ...
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09/24/2018
Die-Stacked DRAM: Memory, Cache, or MemCache?
Die-stacked DRAM is a promising solution for satisfying the ever-increas...
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08/15/2018
Making Belady-Inspired Replacement Policies More Effective Using Expected Hit Count
Memory-intensive workloads operate on massive amounts of data that canno...
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08/14/2018
