research
∙
09/14/2023
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
The increasing popularity of large language models (LLMs) has paved the ...
share
research
∙
10/27/2022
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
Lithography modeling is a crucial problem in chip design to ensure a chi...
research
∙
09/07/2022
TAG: Learning Circuit Spatial Embedding From Layouts
Analog and mixed-signal (AMS) circuit designs still rely on human design...
research
∙
07/08/2022
Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training
Machine learning techniques have been extensively studied for mask optim...
research
∙
03/12/2022
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Lithography simulation is a critical step in VLSI design and optimizatio...
research
∙
03/11/2022
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
In this paper, we present GATSPI, a novel GPU accelerated logic gate sim...
research
∙
02/12/2021
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking
Latency-insensitive design mitigates increasing interconnect delay and e...
research
∙
02/08/2021
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
Quantization enables efficient acceleration of deep neural networks by r...
research
∙
12/19/2020
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification
Vectored IR drop analysis is a critical step in chip signoff that checks...
research
∙
11/26/2020
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
IR drop is a fundamental constraint required by almost all chip designs....
research
∙
11/26/2020
